In a lithography process when a semiconductor device is manufactured, the overlay accuracy between a lower-layer-side pattern formed in a wafer and an upper-layer-side pattern to be formed is important. The reason is that, when the overlay accuracy is reduced, the manufactured semiconductor device does not operate correctly.
In a process of manufacturing the semiconductor device, an error occurs in the formation of films on the front and rear surfaces of the wafer with the progress of the process, which causes a difference in film stress between the front surface and the rear surface. As a result, the wafer warps. When an exposure apparatus zips the warped wafer, the distortion of the wafer is likely to remain, which causes a reduction in the overlay accuracy. Therefore, it is preferable to accurately overlap the layers of the semiconductor device.